\section{Discussion} % (fold)
\label{sec:discussion}


\subsection{Problems} % (fold)

\label{sub:problems}

We had several problems during this assignment, most of them were a direct result of us not doing enough research in the provided material before starting with the implementations. The biggest one was that the processor was \emph{multi cycle}. \\


\subsubsection{Multi cycle}
\label{multi_cycle}
We started off designing the processor as a single cycle unit. Once we started simulating, it became obvious that this was impossible to do because the memory blocks used a whole cycle to fetch data, which resulted in the system being out of sync. Looking for a quick fix, we tried to "hack" the single cycle design into a multi cycle one. By using latches and different ways to route the signals, we attempted to hold on to signals for several cycles until the instructions could be executed. However, this proved to give us more of a headache than we already had, and we decided to redo the design using a state machine, which eventually resolved the whole issue.


\subsubsection{Latency in memory blocks}
\label{latency_in_memory_blocks}

When running the test bench that came supplied with the exercise in an early stage of the implementation, it was clear that the data received from data memory was incorrect. When reading data from data memory the same result was always read twice, even though the instructions run implied that different values should be read for the different instructions.\\



After discussing the problem it became obvious that the memories used an entire cycle for read and write operations. To solve this problem additional functionality had to be added to support delaying the propagation of signals through the processor over several cycles. See section~\ref{state_machine} for the details of the solution.



\subsubsection{Combinatorial operations on the clock}
To implement the required functionality of the processor enable signal sent from the top level, the clock was AND'ed with the \emph{processor\_enable} signal. This new signal was used in the sensitivity list to the process that incremented the PC, and to the one that read from the instruction memory.\\



This worked fine when the system was being simulated, however when the project was to be implemented on the FPGA it turned out that regular signals cannot be used as the clock signal, since the generic hardware cannot handle a clock signal. The clock requires a special line, and must be used directly. The solution to this problem is described in section \ref{sub:implementing_emphprocessor_enable}.

\subsubsection{ModelSim} % (fold)
\label{subsub:modelsim}
In general we struggled a lot with getting useful results from the simulations in ModelSim. This slowed our work some, but after discussing our problems with other groups, and testing out the application, we got up to an acceptable level of efficiency. \\

% subsection modelsim (end)


\subsubsection{VHDL} % (fold)
\label{subsub:vhdl}

The VHDL itself also proved to be a barrier in the beginning. After looking through the code of the supplied components and creating some test components we were able to write code for the functionality required without major problems. \\

% subsection vhdl (end)


\subsection{The exercise} % (fold)
\label{sub:the_exercise}

We found this exercise very fun and interesting, although it should be mentioned that it set a new record in amount of time spent on a single exercise. This was mostly due to us not being familiar with the software tools required, and while this was kind of a pain, we do understand that this is one of the necessities to get a hands-on experience with processor design.\\

Our recommendations would be to follow the same procedure next year, but maybe change assignment 0 to give a more thorough introduction of the software to familiarize the students better with the tools at hand.

% subsection the_excercise (end)
 

% subsection problems (end)


% subsection results (end)

% section discussion (end)